1. Field of the Invention
The present invention relates to a method of processing a wafer to obtain a plurality of devices such as semiconductor chips having through metal electrodes, and more particularly to a technique of forming a rewiring layer on the back side of the wafer.
2. Description of the Related Art
In recent semiconductor device technologies, a semiconductor package having substantially the same size as that of a semiconductor chip called a CSP (Chip Size Package) is effectively used in achieving an increase in packaging density and a reduction in size and thickness. A conventional manufacturing method for such a semiconductor package includes the steps of stacking a semiconductor chip on a package substrate called an interposer, electrically connecting electrodes of the interposer and the semiconductor chip through gold wires by wire bonding, and molding the semiconductor chip and the interposer with resin. There is a case that a rewiring layer is formed on the front side of the semiconductor chip (the device element side). This rewiring layer is formed in the stage of a wafer as an aggregate of semiconductor chips, so that each semiconductor chip has the rewiring layer on the front side thereof.
In the case that the electrodes of the interposer and the semiconductor chip are connected by wire bonding, there is a possibility that the gold wires connecting the electrodes may be deformed in the resin molding step, causing a break or short circuit. In some case, the air remaining in the molding resin may be expanded in heating to cause damage to the semiconductor chip. To cope with this problem, there has been developed a technique of electrical connection such that through electrodes are provided in the semiconductor chip so as to extend through the thickness of the semiconductor chip and to be connected respectively to the electrodes of the semiconductor chip, wherein the electrodes of the semiconductor chip are connected through the through electrodes to the electrodes of the interposer at the same time the semiconductor chip is stacked on the interposer (see Japanese Patent Laid-open No. 2005-136187). Further, since the semiconductor chip is stacked on the interposer in the condition where the front side of the semiconductor chip is pressed toward the interposer, the rewiring layer formed on the front side of the semiconductor chip undergoes the pressure to cause damage such as collapse. To cope with this problem, there has been proposed a technique of forming a rewiring layer on the back side of a semiconductor chip rather than on the front side thereof to thereby reduce a load on the rewiring layer (see Japanese Patent Laid-open No. 2003-017495).
However, the thickness of each semiconductor chip is greatly reduced in the stage of the wafer for the purpose of reducing the size and thickness. Accordingly, handling in shifting the wafer from the thickness reducing step to a subsequent rewiring layer forming step or from the rewiring layer forming step to a subsequent wafer separating step becomes difficult. Further, cracking of the wafer occurs easily to cause a reduction in yield.